The various embodiments of the present invention may be best understood by first describing a structure for a semiconductor memory device. FIG. 5 is a schematic diagram of a semiconductor memory device that includes sense amplifiers that are connected to the bit lines of a memory cell array. The semiconductor memory device is designated by the general reference character 500, and is shown to include a number of memory cells arranged into arrays, two of which are shown as items 502-0 and 502-1. Two memory cells are particularly shown by the reference character 504.
The memory cells 504 can include gates aligned in a row direction (horizontal in the particular view of FIG. 5). Word lines can be commonly connected to the gates within the same row. The word lines for array 502-0 are shown in FIG. 5 as "WL." In this arrangement, cells in a row are selected according to their associated word line. The memory cells 504 can include sources and drains, in which case, such terminals can be aligned in the column direction, connected to a bit line. Bit lines are identified in FIG. 5 as BL1-BL8. Thus, one cell can be selected by a corresponding word line and bit line. For certain memory cell types, the memory cell can be previously charged (or discharged), and thus indicate stored logic values. In addition, the semiconductor memory device 500 may read data from and write data into a selected cell at the same time.
As set forth in FIG. 5, the bit lines (BL1-B8) are connected to sense amplifiers, shown as SA1-SA4. In particular, bit lines BL1 and BL2 are connected to sense amplifier SA1, bit lines BL3 and BL4 are connected to sense amplifier SA2. In addition, bit lines BL5 and BL6 are connected to sense amplifier SA3, and bit lines BL7 and BL8 are connected to sense amplifier SA4.
The sense amplifier arrangement of FIG. 5 can be conceptualized as being disposed in a "zig-zag" manner. That is, the memory cells of the array 502-0 are alternately connected to sense amplifiers SA1 and SA3, which form a sense amplifier column 506-0, and sense amplifiers SA2 and SA4, which form another sense amplifier column 506-1.
A higher-level block diagram of a semiconductor memory device is set forth in FIG. 8. The semiconductor memory device of FIG. 8 is designated by the general reference character 800, and which is shown to include sense amplifier columns 802-0 to 802-2 alternately disposed between memory cell arrays 804-0 to 804-2. Sense amplifier columns (802-0 to 802-2) are shown to be connected to corresponding sense amplifier selecting circuits, shown as 808-0 to 808-2. The sense amplifier columns (802-0 to 802-2) are also shown to be connected to the bit lines BL of the memory cell arrays (804-1 to 804-2).
Sense amplifier selecting circuits (808-0 to 808-2) select sense amplifiers within the sense amplifier columns (802-0 to 802-2).
In addition to being connected to the sense amplifier columns (802-0 to 802-2) by bit lines, the memory cell arrays (804-0 to 804-2) are also shown to be connected to decoders 806-0 to 806-2 by word lines (shown as "WL"). The decoders (806-0 to 806-2) select cells in the row direction by selecting word lines.
The general arrangement of the sense amplifier selecting circuits (808-0 to 808-2) is illustrated in FIG. 8 by sense amplifier selecting circuits 808-1 and 808-2. Sense amplifier selecting circuit 804-1 is shown to include two NAND gates (808-00 and 808-01), a NOR gate 810-0, two inverters (812-00 and 812-01), a p-type transistor 814-0, and an n-type transistor 816-0. In the same general fashion, sense amplifier selecting circuit 808-2 is shown to include two NAND gates (808-10 and 808-11), a NOR gate 810-1, two inverters (812-10 and 812-11), a p-type transistor 814-1, and an n-type transistor 816-1.
The general operation of sense amplifier selecting circuit 808-1 will now be described. The sense amplifier selecting circuit 808-1 receives a block select signal A1 as an input The block select signal Gal is applied to NAND gate 808-00, which provides a select signal BSEL1 as an output. Accordingly, when the A1 signal is active (all inputs to NAND gate 808-00 are high) the BSEL1 signal is driven low. The BSEL1 signal is shown to be applied to sense amplifier column 802-1 and NAND gate 808-01. According to the BSEL1 signal tig, and other select signals (not shown) a word line is selected by decoder 806-0. The selected word line results in the selection of a memory cell row within memory cell array 804-0.
Continuing with the description of sense amplifier selecting circuit 808-1, in response to a low BSEL1 signal the NAND gate 808-01 output is driven high. The high value is inverted by inverter 812-00 and applied as an input to NOR gate 810-0. NOR gate 810-0 receives a sense signal SENS as another input. Thus, when the SENS signal and the output of inverter 810-0 are both low, the output of NOR gate 810-0 will be driven high. This value will be inverted by inverter 812-01 and applied to the gate of transistor 814-0. Transistor 814-0 will be turned on, resulting in drive signal SAP-0 being driven high. At the same time, the high output from NOR gate 810-0 is also applied to the gate of transistor 816-0, resulting in drive signal SAN-0 being driven low.
The high SAP-0 and low SAN-0 signals result in a sense amplifier within the sense amplifier column 802-1 being selected. For example, if reference is made to FIG. 5, sense amplifiers corresponding to SA2 or SA4 could be selected. Because a word line within memory cell array 804-0 has been previously selected, the selection of a sense amplifier results in the selection of a memory cell coupled to a bit line associated with the selected sense amplifier.
Sense amplifier selecting circuit 808-2 operates in a similar fashion to sense amplifier select circuit 804-1. Within sense amplifier select circuit 808-2, a block select signal A2 is applied to NAND gate 808-10. When the A2 signal is active, the output of NAND gate 808-10 (select signal BSEL2) will be low. The low BSEL2 signal will be applied to sense amplifier column 802-2. According to the BSEL2 signal timing, and other select signals (not shown), a word line is selected by decoder 806-1, resulting in the selection of a memory cell row within memory cell array 804-1. In response to a low BSEL2 signal, NAND gate 808-11 output is driven high, resulting in a low input to NOR gate 810-1. NOR gate 810-1 also receives a sense signal SENS as an input. Thus, in a similar fashion to the sense amplifier selecting circuit 808-1, a low SENS signal and active A2 signal will resulting in a drive signal SAP-1 that is high, and a drive signal SAN-1 that is low.
The high SAP-1 and low SAN-1 signals result in a sense amplifier within the sense amplifier column 802-2 being selected. For example, if reference is made to FIG. 5, the sense amplifier corresponding to SA2 or SA4 could be selected.
It is noted that the BSEL2 signal provided by NAND gate 808-10 is also applied to sense amplifier selecting circuit 808-1 and hence affects the operation of sense amplifier column 802-1. As a result, in addition to the selection of a sense amplifier within sense amplifier column 802-2 (such as sense amplifier SA2 or SA4 for an arrangement like FIG. 5), an active BSEL2 signal also selects a sense amplifier within sense amplifier column 802-1 (such as sense amplifier SA1 or SA3 for an arrangement like FIG. 5). Because a word line within memory cell array 804-1 has been previously selected, the selection of a sense amplifier within sense amplifier column 802-1 results in the selection of a memory cell. In this way, an active A2 signal and SENS signal will select sense amplifiers in both sense amplifier columns 802-1 and 802-2.
Referring now to FIG. 9, a sense amplifier column is illustrated in a schematic diagram. The sense amplifier column is designated by the general reference character 900, and is shown to include a sense amplifier 902 coupled to bit lines BL1 and BL2. The sense amplifier 902 includes two p-channel transistors 904-0 and 904-1, and two n-channel transistors 906-0 and 906-1. A node 908-0 between transistors 904-0 and 906-0 is coupled to bit line BL1, and forms one output for the sense amplifier 902. A node 908-1 between transistors 904-1 and 906-1 is coupled to bit line BL2, and forms another output for the sense amplifier 902. The SAP signal is applied to a drive node 910-0 common to transistors 904-0 and 904-1, and the SAN signal is applied to a drive node 910-1 common to transistors 906-0 and 906-1.
FIG. 9 also includes a select (and/or precharge) signal BSEL1a that is coupled to a first set of n-channel precharge transistors (912-0 to 912-2) and a second set of n-channel precharge transistors (912-3 to 912-5). When the BSEL1a signal is low, the precharge transistors 912-0 to 912-5 are disabled, allowing sense amplifier 902 to be selected.
The sense amplifier column 900 is also shown to receive separation signals TG0 and TG1. Separation signal TG1 is applied to n-channel transistors 914-0 and 914-1, which connect an upper portion (with respect to FIG. 9) of bit lines BL1 and BL2 to sense amplifier 902. Separation signal TG0 is applied to n-channel transistors 914-2 and 914-3, which connect a lower portion (with respect to FIG. 9) of bit lines BL1 and BL2 to sense amplifier 902. Separation signals TG0 and TG1 allow a selected memory cell to be separated from a non-selected memory cell. For example, if a word line results in a memory cell being coupled to the upper portion of bit lines BL1 and BL2, signal TG1 will be high to connect the memory cell to the sense amplifier 902. Signal TG0 will be low, to isolate non-selected memory cells coupled to the lower portion of bit lines BL1 and BL2.
Referring now to FIG. 10, a timing diagram is set forth illustrating the selection of a memory cell in a semiconductor memory device. FIG. 10 includes a number of signals, including a select/precharge signal BSEL, a word line signal WL, complementary drive signals SAP and SAN, a bit line pair response BL, and a cell node response CELL NODE. The cell node response illustrates a possible response of a data providing node on a selected memory cell.
At time t1, the BSEL signal transitions low, disabling precharge circuitry and allowing a sense amplifier to be selected. At time t2, a word line signal WL transitions high, representing the selection of a word line in a memory cell array. The selection of a word line results in a memory cell placing data on bit line pair BL. Thus, at time t2, the BL waveform begins to separate while the CELL NODE waveforms converge.
At time t3, with the input of an active sense signal SENS, the SAP signal goes high and the SAN signal goes low. As a result, the data signal on the bit line pair BL is further driven to high and low levels. The high and low BL levels charge the memory cell to a particular logic level, as illustrated by the waveforms of CELL NODE.
At time t4, the WL signal returns low, de-selecting the word line. Thereafter, at about time t5, the SAP and SAN signals return to an intermediate value and the BSEL signal returns high. This results in the bit lines BL being equalized (and/or precharged) to an intermediate level.
While the sense amplifier column arrangement of FIG. 9 provides for the selection of memory cells, the use of the TG1 and TG0 signals, which results in the separation of a selected memory cell from a non-selected memory cell, can introduce unwanted delay into the operation of a memory device. In particular, an arrangement such as that set forth in FIG. 9 may result in a delay in the propagation of a data signal from a memory cell array to the sense amplifier. For this reason, sense amplifier column arrangements that eliminate the use of TG1 and TG0 signals can be employed. An example of such a circuit is set forth in FIG. 3.
FIG. 3 illustrates a sense amplifier column 300 that does not utilize TG0 and TG1 signals. The sense amplifier column 300 includes a sense amplifier 302 having two p-channel transistors 304-0 and 304-1 and two n-channel transistors 306-0 and 306-1. In addition, precharge transistors 308-0 to 308-2 receive a select signal BSEL. In this arrangement, the BSEL signal must be operative (low in this particular example) for accesses to both an upper memory cell array (which would be coupled to the upper portion of bit lines BL1/BL2) and a lower memory cell array (which would be coupled to the lower portion of bit lines BL1/BL2). For this reason, the generation of the BSEL signal will differ from the generation of the precharge signals BSEL1 and BSEL2 of FIG. 8. In particular, one way to generate a BSEL for such a sense amplifier column, would be to utilize the output of inverters, shown as 812-00 and 812-10 in FIG. 8. The output that may be used as a BSEL signal is indicated by the letter "Z" in FIG. 8.
In addition, in the event sense amplifier columns, such as that set forth in FIG. 3, were to be used in the architecture of FIG. 8, the sense amplifier selecting circuits would operate in a different fashion. In particular, those NAND gates (808-00 and 808-10) within each sense amplifier selecting circuit (808-0 to 808-2) that receive block select signals (A1 and A2) would decode combinations of all block decode signals to generate an associated BSEL signal. The BSEL signals would then be generated from the output signals shown as Z, as described above. An example of such a block decoding arrangement is set forth in FIG. 7a.
FIG. 7a is a table illustrating a block decoding scheme. If it is assumed that the block addresses for the sense amplifier columns are given as X5 to X0, each different combination of X5 to X0 values will result in the activation of a different BSEL signal. For example, if values X5 to X0 are "111111" an active BSEL0 signal is output. When the X5 to X0 values are "111110," an active BSEL1 signal is output. In addition, X5 to X0 values of "111101" result in the output of an active BSEL2 signal, and when the X5 to X0 values are "111100," an active BSEL3 signal is output.
One way to generate the decoding operation set forth in FIG. 7a is set forth in schematic diagrams in FIGS. 7b and 7c. FIG. 7c illustrates how various values can be logically multiplied together to generate initial decoded values. FIG. 7c includes four circuits for accomplishing the logical multiplication, each circuit including a NAND gate (700-0 to 700-3) having an output coupled to an inverter (702-0 to 702-3). The various combinations of X0 and X1 values are logically multiplied together in FIG. 7c. In particular, the X0 and X1 values are multiplied together to generate a value X0T1T. The X0 and /X1 values (/X1 being the logical inverse of X1) are multiplied together to generate a value X0T1N. The /X0 and X1 values are multiplied to generate a value X0N1T, and the /X0 and /X1 values are multiplied together to generate a X0N1N value. In the same general fashion, the X2, /X2, X3, and /X3 values can be multiplied together, and the X4, /X4, X5 and /X5 values can be multiplied together.
The logically multiplied value pairs (which can be conceptualized as decoded values) can then be applied to additional logic to generate select signals, such as the signal Z of FIG. 8. The generation of such a signal is set forth in a circuit in FIG. 7b. FIG. 7b is a circuit that can be included within a sense amplifier selecting circuit, such as 808-1 in FIG. 8. The circuit of FIG. 7b generates a BSEL1 signal, and is shown to include three NAND gates (704-0 to 704-2) and an inverter 706. NAND gate 704-0 receives logically multiplied pairs X0T1T, X2T3T, and X4T5T as inputs, while NAND gate 704-1 receives logically multiplied pairs X0N1T, X2T3T and X4T5T. The outputs of NAND gates 704-0 and 704-1 are applied as inputs to NAND gate 704-2. The output of NAND gate 704-2 is inverted by inverter 706 to generate the BSEL1 signal. NAND gates 704-0 and 704-1 can be conceptualized as corresponding to NAND gate 808-00, NAND gate 704-2 can be conceptualized as corresponding to NAND gate 808-01, and inverter 706 can be conceptualized as corresponding to inverter 812-00.
The approach set forth in FIGS. 3 and 7 can improve the speed of a semiconductor memory device by eliminating the use of TG0 and TG1 signals, and thereby improve the speed at which a data signal from a memory array can propagate to a sense amplifier. However, such an approach is achieved at the cost of a complicated decoding scheme, such as that set forth in FIG. 7b. The speed advantages can thus be offset by the added circuitry required for decoding.
It would be desirable to provide some way of generating a select signal, such as the BSEL signals described above, that does not require as complex a logic arrangement such as that set forth in FIGS. 7b and 7c.